tlb

Every memory access in a paged system requires a page table lookup (extra memory access), making every reference 2x slower. We need to cache recent translations.

TLB is a hardware cache that stores recent virtual-to-physical page translations, making address translation O(1) in the common case.

1. CPU generates virtual address
2. TLB checked first (parallel lookup, very fast)
3. If TLB hit: use cached frame number directly
4. If TLB miss: do page table walk, update TLB
5. Access memory with physical address

• Hit rate typically >95% for well-behaved programs
• Hardware-managed (some architectures) or software-managed (MIPS)
• TLB flush on context switch (different process = different pages)
• Small but very fast (32-1024 entries typical)

• Built from: Paging, Page Table
• Builds into: Virtual Memory
• Related: CPU Cache, Address Translation
• Contrasts with: Page Table (cache vs backing store)

• TLB flush on context switch hurts performance
• Some entries can be wired (never flushed, for kernel)
• TLB miss handling is in hardware or software depending on architecture