In paging, processes use virtual (logical) addresses, but RAM uses physical addresses. The CPU needs to know which physical frame corresponds to each virtual page.
A page table is a data structure maintained by the OS that maps each virtual page of a process to its physical frame in RAM.
- CPU generates logical address: page number + page offset
- Page number is used as index into page table
- Page table entry gives frame number
- Physical address = frame number × page size + offset
- One page table per process
- Stored in RAM (not in CPU registers — too large)
- Accessed on every memory reference (needs caching → TLB)
- Can be single-level, multi-level, or inverted
- Built from: Paging, Virtual Memory
- Builds into: TLB, Demand Paging
- Related: Multi-Level Page Table, Inverted Page Table
- Contrasts with: Segment Table (variable sizes vs fixed pages)
- Single-level page table can be huge (1M entries for 4GB process with 4KB pages)
- Multi-level page tables add levels of indirection
- Page table walks are slow (4 memory accesses for 4-level paging)