Even Cycle Stealing Mode can interrupt CPU work. For systems where CPU responsiveness is critical and DMA transfers are large, we need a mode where DMA is truly “transparent” to the CPU — no interference at all.
Transparent Mode DMA only transfers data when the CPU is not using the system bus, making the DMA operation completely invisible to the CPU with zero performance impact.
- DMA controller monitors CPU bus usage
- When CPU is not accessing memory (e.g., executing from cache, doing register-only ops), DMA transfers one byte/word
- If CPU needs the bus, DMA immediately releases it
- DMA resumes when bus becomes free again
- Transfer continues opportunistically until complete
- Slowest DMA mode (limited by CPU idle bus time)
- Zero CPU overhead — completely transparent to CPU
- Most complex to implement (needs bus monitoring logic)
- Best for background transfers where speed doesn’t matter but CPU responsiveness does
- Built from: DMA, DMA Controller
- Contrasts with: Burst Mode DMA — CPU fully blocked, fastest transfer
- Contrasts with: Cycle Stealing Mode DMA — CPU can work between transfers, but still interrupted
- Related: CPU, System Bus
- Very slow for large transfers if CPU is constantly busy with memory accesses
- Complex hardware required to monitor bus usage and arbitrate fairly
- Not suitable for time-critical transfers (no guaranteed completion time)
- May never complete if CPU never releases bus (starvation)