Memory accesses are slow (tens to hundreds of CPU cycles). Accessing operands from memory for every instruction would severely limit CPU performance. We need faster storage for frequently used values.
Register Addressing specifies a CPU register as the operand location. The CPU reads/writes the register directly — no memory access needed, making it the fastest addressing mode.
- Instruction specifies register name (e.g., AX, BX, R1, R2)
- CPU accesses the named register in the register file
- No memory access required — registers are inside CPU
- Example:
MOV AX, BX— copies content of BX into AX - Typically 2-3 cycle operation (fetch, decode, execute)
- Fastest addressing mode (no memory access, registers are in CPU)
- Limited number of registers (typically 16-32 general-purpose registers)
- Used for temporary values, loop counters, frequently accessed data
- RISC relies heavily on register addressing (load-store architecture)
- Built from: Addressing Mode, CPU Register
- Contrasts with: Immediate Addressing — constant in instruction, not register
- Related: Register File, Load-Store Architecture
- Builds into: Arithmetic Instruction — typically uses register operands
- Limited registers — compiler must manage register allocation carefully
- Register spilling: when no free registers, must spill to memory (slow)
- Some ISAs have special registers (stack pointer, program counter) with restrictions