A CPU instruction takes multiple steps (fetch, decode, execute, memory, writeback). If we wait for one instruction to finish before starting the next, the CPU is mostly idle — each stage is only used 1/5 of the time.
Pipelining overlaps multiple instructions in execution — while one instruction is executing, the next is being decoded, and the one after is being fetched, like an assembly line.
- Divide instruction execution into stages: IF (fetch) → ID (decode) → EX (execute) → MEM (memory) → WB (writeback)
- Each stage processes a different instruction simultaneously
- New instruction enters pipeline each clock cycle (after pipeline is full)
- Throughput = 1 instruction per cycle (after initial fill)
- RISC pipelines easily (fixed-length, simple instructions); CISC harder (variable-length, multi-cycle)
- Throughput up to 1 instruction per clock cycle (ideal case)
- RISC enables easy pipelining (fixed-length, simple instructions)
- Pipeline depth: more stages = finer granularity but more overhead
- Hazards can stall pipeline: data hazards, control hazards, structural hazards
- Built from: RISC Architecture, Clock Cycle
- Contrasts with: CISC Architecture — harder to pipeline due to complex instructions
- Related: Instruction Set, CPU
- Builds into: Superscalar — multiple pipelines in parallel
- Pipeline stalls: when next instruction can’t proceed (dependencies, branches)
- Branch prediction: need to guess which way a branch goes to keep pipeline full
- Pipeline flush: when a branch is mispredicted, partially executed instructions must be discarded
- RISC pipelines are deeper (more stages) than CISC (which are often translated to micro-ops first)