/wiki / computer-architecture

arithmetic-instruction

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[arithmetic-instruction]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of arithmetic instruction.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Arithmetic Instruction

Connections

Related: Index — auto stub for singleton [[arithmetic-instruction]] from wiki/computer-architecture/register-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

arm-architecture

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[arm-architecture]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of arm architecture.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Arm Architecture

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/risc-vs-cisc.md, wiki/computer-architecture/risc-architecture.md

Edge Cases & Gotchas

To be written.
To be written.

array

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[array]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of array.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Array

Connections

Related: Index — auto stub for singleton [[array]] from wiki/computer-architecture/indexed-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

branch-instruction

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[branch-instruction]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of branch instruction.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Branch Instruction

Connections

Related: Index — auto stub for singleton [[branch-instruction]] from wiki/computer-architecture/relative-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

clock-cycle

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[clock-cycle]] — needs human content. This page was referenced 3 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of clock cycle.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Clock Cycle

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/cisc-architecture.md, wiki/computer-architecture/risc-architecture.md

Edge Cases & Gotchas

To be written.
To be written.

cpu-register

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[cpu-register]] — needs human content. This page was referenced 3 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of cpu register.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Cpu Register

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/register-addressing.md, wiki/computer-architecture/indirect-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

data-serialization

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[data-serialization]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of data serialization.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Data Serialization

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/endianness.md, wiki/computer-architecture/network-byte-order.md

Edge Cases & Gotchas

To be written.
To be written.

function-call

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[function-call]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of function call.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Function Call

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/stack-addressing.md, wiki/computer-architecture/relative-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

function-parameters

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[function-parameters]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of function parameters.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Function Parameters

Connections

Related: Index — auto stub for singleton [[function-parameters]] from wiki/computer-architecture/stack-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

instruction-set-architecture

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[instruction-set-architecture]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of instruction set architecture.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Instruction Set Architecture

Connections

Related: Index — auto stub for singleton [[instruction-set-architecture]] from wiki/computer-architecture/instruction-set.md

Edge Cases & Gotchas

To be written.
To be written.

intel-cpu

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[intel-cpu]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of intel cpu.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Intel Cpu

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/cisc-architecture.md, wiki/computer-architecture/little-endian.md

Edge Cases & Gotchas

To be written.
To be written.

jump-instruction

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[jump-instruction]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of jump instruction.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Jump Instruction

Connections

Related: Index — auto stub for singleton [[jump-instruction]] from wiki/computer-architecture/relative-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

load-store-architecture

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[load-store-architecture]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of load store architecture.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Load Store Architecture

Connections

Related: Index — auto stub for singleton [[load-store-architecture]] from wiki/computer-architecture/register-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

loop

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[loop]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of loop.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Loop

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/indexed-addressing.md, wiki/computer-architecture/relative-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

micro-ops

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[micro-ops]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of micro ops.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Micro Ops

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/cisc-architecture.md, wiki/computer-architecture/risc-vs-cisc.md

Edge Cases & Gotchas

To be written.
To be written.

mips-architecture

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[mips-architecture]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of mips architecture.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Mips Architecture

Connections

Related: Index — auto stub for singleton [[mips-architecture]] from wiki/computer-architecture/risc-architecture.md

Edge Cases & Gotchas

To be written.
To be written.

motorola-68k

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[motorola-68k]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of motorola 68k.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Motorola 68k

Connections

Related: Index — auto stub for singleton [[motorola-68k]] from wiki/computer-architecture/big-endian.md

Edge Cases & Gotchas

To be written.
To be written.

multi-byte-data

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[multi-byte-data]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of multi byte data.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Multi Byte Data

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/endianness.md, wiki/computer-architecture/endianness-comparison.md

Edge Cases & Gotchas

To be written.
To be written.

opcode

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[opcode]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of opcode.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Opcode

Connections

Related: Index — auto stub for singleton [[opcode]] from wiki/computer-architecture/operand.md

Edge Cases & Gotchas

To be written.
To be written.

pointer

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[pointer]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of pointer.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Pointer

Connections

Related: Index — auto stub for singleton [[pointer]] from wiki/computer-architecture/indirect-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

pop-instruction

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[pop-instruction]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of pop instruction.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Pop Instruction

Connections

Related: Index — auto stub for singleton [[pop-instruction]] from wiki/computer-architecture/stack-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

program-counter

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[program-counter]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of program counter.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Program Counter

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/immediate-addressing.md, wiki/computer-architecture/relative-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

push-instruction

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[push-instruction]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of push instruction.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Push Instruction

Connections

Related: Index — auto stub for singleton [[push-instruction]] from wiki/computer-architecture/stack-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

register-file

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[register-file]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of register file.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Register File

Connections

Related: Index — auto stub for singleton [[register-file]] from wiki/computer-architecture/register-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

sparc

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[sparc]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of sparc.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Sparc

Connections

Related: Index — auto stub for singleton [[sparc]] from wiki/computer-architecture/big-endian.md

Edge Cases & Gotchas

To be written.
To be written.

stack-frame

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[stack-frame]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of stack frame.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Stack Frame

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/stack-addressing.md, wiki/computer-architecture/register-indirect-with-displacement.md

Edge Cases & Gotchas

To be written.
To be written.

stack-pointer

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[stack-pointer]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of stack pointer.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Stack Pointer

Connections

Related: Index — auto stub for singleton [[stack-pointer]] from wiki/computer-architecture/stack-addressing.md

Edge Cases & Gotchas

To be written.
To be written.

stack

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[stack]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of stack.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Stack

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/stack-addressing.md, wiki/computer-architecture/register-indirect-with-displacement.md

Edge Cases & Gotchas

To be written.
To be written.

struct

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[struct]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of struct.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Struct

Connections

Related: Index — auto stub for singleton [[struct]] from wiki/computer-architecture/register-indirect-with-displacement.md

Edge Cases & Gotchas

To be written.
To be written.

superscalar

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for singleton broken link [[superscalar]] — referenced once and was missing. Keeps graph connected per AGENTS.md:199.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of superscalar.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Superscalar

Connections

Related: Index — auto stub for singleton [[superscalar]] from wiki/computer-architecture/pipelining.md

Edge Cases & Gotchas

To be written.
To be written.

tcp-ip-model

2026-09-19T00:00:00.000Z

The Problem

Auto-created stub for broken link [[tcp-ip-model]] — needs human content. This page was referenced 2 times and was missing, so a stub was created to keep the graph connected.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation of tcp ip model.

How It Works

To be written.
To be written.
To be written.
To be written.

Visual Explanation

Semantic Network

Key Properties

To be written.

Real-World Example

# TODO: add example for Tcp Ip Model

Connections

Related: Index — auto stub, needs proper links to wiki/computer-architecture/network-byte-order.md, wiki/cn/layered-model.md

Edge Cases & Gotchas

To be written.
To be written.

effective-address

2026-09-02T00:00:00.000Z

draft: true

The Problem

Auto-created stub for broken link [[effective-address]] — needs human content.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation.

How It Works

To be written.

Visual Explanation

digraph effective-address {
  rankdir=LR
  node [shape=box style=filled fillcolor="#f0f4ff" fontname="Helvetica"]
  A [label="Stub: effective-address"]
  B [label="To be written"]
  A -> B [label="needs content"]
}

Semantic Network

graph semantic_effective-address {
  layout=neato
  node [shape=ellipse fontname="Helvetica" fontsize=11 style=filled]
  THIS [label="effective address" fillcolor="#ffd700" fontsize=13 style="filled,bold"]
  REL1 [label="Related" fillcolor="#f0f0f0"]
  THIS -- REL1 [label="related"]
}

Key Properties

To be written.

Real-World Example

# TODO: add example

Connections

Related: Index — auto stub, needs proper links

Edge Cases & Gotchas

To be written.

Computer Architecture -- Map of Content

2026-09-02T00:00:00.000Z

Map of Content for Computer Architecture — 29 concepts. Start here to navigate computer-architecture.

Core Concepts

Addressing Mode — concept
addressing-modes-compared — concept
Big Endian — concept
Burst Mode DMA — concept
CISC Architecture — concept
Cycle Stealing Mode DMA — concept
Direct Addressing — concept
DMA Controller — concept
dma-modes-comparison — concept
endianness-comparison — concept
Endianness — concept
Immediate Addressing — concept
Indexed Addressing — concept
Indirect Addressing — concept
Instruction Set — concept
Little Endian — concept
Multi-Channel DMA — concept
Network Byte Order — concept
Operand — concept
Pipelining — concept
O — concept
Register Addressing — concept
Register Indirect with Displacement — concept
Relative Addressing — concept
RISC Architecture — concept
risc-vs-cisc — concept
Single-Channel DMA — concept
Stack Addressing — concept
Transparent Mode DMA — concept

Mechanisms & How Things Work

Pages that explain processes/flows.

Comparisons & Tradeoffs

(No synthesis yet — create via ingest or query —save)

memory-address

2026-09-02T00:00:00.000Z

draft: true

The Problem

Auto-created stub for broken link [[memory-address]] — needs human content.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation.

How It Works

To be written.

Visual Explanation

digraph memory-address {
  rankdir=LR
  node [shape=box style=filled fillcolor="#f0f4ff" fontname="Helvetica"]
  A [label="Stub: memory-address"]
  B [label="To be written"]
  A -> B [label="needs content"]
}

Semantic Network

graph semantic_memory-address {
  layout=neato
  node [shape=ellipse fontname="Helvetica" fontsize=11 style=filled]
  THIS [label="memory address" fillcolor="#ffd700" fontsize=13 style="filled,bold"]
  REL1 [label="Related" fillcolor="#f0f0f0"]
  THIS -- REL1 [label="related"]
}

Key Properties

To be written.

Real-World Example

# TODO: add example

Connections

Related: Index — auto stub, needs proper links

Edge Cases & Gotchas

To be written.

x86-architecture

2026-09-02T00:00:00.000Z

draft: true

The Problem

Auto-created stub for broken link [[x86-architecture]] — needs human content.

Formal Definition

Per Wikipedia: “To be written.”

Explanation

Stub — fill with plain language explanation.

How It Works

To be written.

Visual Explanation

digraph x86-architecture {
  rankdir=LR
  node [shape=box style=filled fillcolor="#f0f4ff" fontname="Helvetica"]
  A [label="Stub: x86-architecture"]
  B [label="To be written"]
  A -> B [label="needs content"]
}

Semantic Network

graph semantic_x86-architecture {
  layout=neato
  node [shape=ellipse fontname="Helvetica" fontsize=11 style=filled]
  THIS [label="x86 architecture" fillcolor="#ffd700" fontsize=13 style="filled,bold"]
  REL1 [label="Related" fillcolor="#f0f0f0"]
  THIS -- REL1 [label="related"]
}

Key Properties

To be written.

Real-World Example

# TODO: add example

Connections

Related: Index — auto stub, needs proper links

Edge Cases & Gotchas

To be written.

addressing-mode

2026-04-30T00:00:00.000Z

The Problem

CPU instructions need to know where to find their operands (the data they operate on). Operands could be in registers, memory, or embedded in the instruction itself. How does the CPU know which one?

Core Idea

Addressing Mode defines how a CPU instruction specifies the location of its operands — whether in registers, memory, or as immediate values embedded in the instruction.

How It Works

Instruction encoding includes opcode (what to do) and addressing mode specifier (where data is)
CPU decodes the addressing mode to determine how to fetch operands
Different modes: immediate (value in instruction), register (in register), direct (memory address in instruction), etc.
Complex modes combine: base + index, base + displacement
Programmer/compiler chooses addressing mode based on data location and access pattern

Key Properties

Makes CPU instructions flexible and powerful
Different modes for different use cases (constants, arrays, structs, etc.)
More addressing modes = more complex instruction decoding
Choice of addressing mode affects instruction length and execution speed

Semantic Network

Connections

Built from: Instruction Set, CPU, Operand
Builds into: Immediate Addressing, Register Addressing, Direct Addressing
Builds into: Indirect Addressing, Indexed Addressing
Related: Effective Address, Memory Address

Edge Cases & Gotchas

More addressing modes = more complex hardware (decoder logic)
Some modes are slower (indirect, indexed) due to extra memory accesses
Not all CPUs support all addressing modes (RISC typically has fewer)
Invalid addressing mode encoding causes illegal instruction exception

Addressing Modes Compared -- Usage and Trade-offs

2026-04-30T00:00:00.000Z

The Comparison

Different addressing modes exist to efficiently access data in different scenarios: constants, registers, fixed memory locations, arrays, structs, and control flow.

Side-by-Side Comparison

Mode	Operand Location	Example	Speed	Use Case
Immediate	In instruction (constant)	MOV AX, 5	Fastest (no mem access)	Constants, initialization
Register	CPU register	MOV AX, BX	Fastest (no mem access)	Temp values, frequent access
Direct	Fixed memory address	MOV AX, [1234h]	Fast (1 mem access)	Global variables
Indirect	Address in register	MOV AX, [BX]	Medium (2 mem accesses)	Pointers, dynamic data
Indexed	Base + index register	MOV AX, [1000h+SI]	Medium (calc + mem)	Arrays, tables
Register+Disp	Register + constant	MOV AX, [BX+4]	Medium (calc + mem)	Struct fields, stack vars
Relative	PC + offset	JMP 10	Medium (calc + mem)	Branches, jumps
Stack	Top of stack	PUSH AX, POP BX	Fast (SP is register)	Function calls, expressions

Key Insights

Fastest modes: Immediate and Register addressing (no memory access beyond instruction fetch).
Most flexible: Indirect, Indexed, and Register+Displacement enable dynamic data access (arrays, structs, pointers).
Control flow: Relative addressing is essential for position-independent code (branches, function calls).
Stack addressing: Implicit addressing (no address in instruction) — used for function calls, local variables, expression evaluation.
Trade-off: More complex addressing = more hardware (address calculation logic) but more flexible programs.

Visual Explanation

Semantic Network

Connections

Immediate Addressing — constants in instruction
Register Addressing — operands in registers
Direct Addressing — fixed memory address
Indirect Addressing — address in register
Indexed Addressing — base + index for arrays
Register+Displacement — struct fields
Relative Addressing — PC-relative branches
Stack Addressing — stack operations

big-endian

2026-04-30T00:00:00.000Z

The Problem

When storing multi-byte values in memory, we need a consistent convention for byte order. Some systems store the most significant byte first to match human reading order.

Core Idea

Big Endian stores the Most Significant Byte (MSB) at the lowest memory address, with remaining bytes stored in decreasing significance order.

How It Works

Take a 32-bit number: 0x12345678 (bytes: 12=MSB, 34, 56, 78=LSB)
Store MSB (0x12) at lowest address (e.g., 1000h)
Store next byte (0x34) at next address (1001h)
Continue until LSB (0x78) at highest address (1003h)
Memory dump reads left-to-right like human writing: 12 34 56 78

Key Properties

Matches human reading order (easier to debug in memory dumps)
Standard for network protocols (TCP/IP uses Big Endian = “network byte order”)
Used by: Motorola 68k, SPARC (sometimes), PowerPC (can be bi-endian)
Easier to interpret hex dumps visually

Semantic Network

Connections

Contrasts with: Little Endian — stores LSB first
Built from: Endianness, Memory
Builds into: Network Byte Order — TCP/IP mandates Big Endian
Related: Motorola 68k, Sparc

Edge Cases & Gotchas

Less efficient for x86 CPUs (must convert to Little Endian for arithmetic)
Conversion needed when receiving network data on Little Endian systems
Not all RISC chips use Big Endian (ARM is Little Endian, MIPS can be either)

burst-mode-dma

2026-04-30T00:00:00.000Z

The Problem

DMA transfers need to balance between fast data movement and not blocking the CPU. If the DMA controller transfers too slowly, the I/O device may underrun; if it hogs the bus, the CPU can’t work.

Core Idea

Burst Mode DMA transfers the entire block of data in one continuous operation, with the DMA controller holding exclusive control of the system bus until the transfer completes.

How It Works

DMA controller requests and gains exclusive bus control
Entire data block is transferred continuously, one word/byte at a time
CPU is paused/halted during the entire transfer — cannot access memory or bus
When transfer completes, DMA releases the bus and sends interrupt to CPU

Key Properties

Fastest DMA mode for the transfer itself — no interruptions
CPU is completely blocked during transfer (can’t even access cache if it misses)
Best for high-priority, time-sensitive transfers (real-time systems)
Simple to implement — no need for interleaving logic

Semantic Network

Connections

Built from: DMA, DMA Controller
Contrasts with: Cycle Stealing Mode DMA — CPU can work between transfers
Contrasts with: Transparent Mode DMA — DMA only runs when CPU not using bus
Related: Polling — CPU also blocked in polling, but for different reasons

Edge Cases & Gotchas

Long bursts can cause CPU starvation — system becomes unresponsive
Not suitable for systems requiring low-latency CPU response
Some systems limit maximum burst size to prevent excessive CPU blocking
Cache coherency issues still apply — CPU cache may be stale after burst

cisc-architecture

2026-04-30T00:00:00.000Z

The Problem

Early CPUs had few registers and slow memory. To make programming easier and code smaller, can we put complex operations (like “load, add, store” all in one instruction) directly in hardware?

Core Idea

CISC (Complex Instruction Set Computer) uses a large set of complex instructions where a single instruction can perform multi-step operations (e.g., load from memory, add, and store — all in one instruction).

How It Works

CPU has a large set of instructions (hundreds), some very complex
Instructions have variable length (1 to 15+ bytes) — harder to decode
Complex instructions take multiple clock cycles to execute
Hardware handles complex operations — less work for compiler/software
Fewer instructions per program, but each instruction does more work

Key Properties

Large instruction set (hundreds of instructions)
Variable instruction length (1-15+ bytes, harder to decode)
Multiple clock cycles per instruction
Complex hardware (more transistors, harder to design)
Smaller programs (fewer instructions needed)

Semantic Network

Connections

Contrasts with: RISC Architecture — simple instructions, software does more work
Built from: CPU, Instruction Set, Clock Cycle
Builds into: Micro-ops — modern x86 translates CISC to RISC-like internally
Related: x86 Architecture, Intel CPU

Edge Cases & Gotchas

Pipelines are harder to implement due to variable instruction length
Slower clock speeds due to complex hardware
Many instructions are rarely used (wasted silicon)
Modern x86 CPUs are “RISC inside” — they translate CISC instructions to micro-ops

cycle-stealing-mode-dma

2026-04-30T00:00:00.000Z

The Problem

Burst Mode DMA blocks the CPU entirely during transfer, which can cause system unresponsiveness. But we still want DMA’s benefit of freeing the CPU from handling each byte. We need a middle ground.

Core Idea

Cycle Stealing Mode DMA transfers one byte or word at a time, then releases the bus to let the CPU run momentarily between transfers, balancing throughput with CPU responsiveness.

How It Works

DMA controller takes bus, transfers one byte/word
DMA releases bus to CPU
CPU can access memory/run for a few cycles
DMA requests bus again, transfers next byte/word
Repeat until entire block is transferred

Key Properties

Slower than burst mode (more bus arbitration overhead per byte)
CPU is not fully halted — can respond to interrupts, do useful work
Good balance between transfer speed and system responsiveness
Most common DMA mode in general-purpose systems

Semantic Network

Connections

Built from: DMA, DMA Controller
Contrasts with: Burst Mode DMA — CPU fully blocked during transfer
Contrasts with: Transparent Mode DMA — DMA only runs when CPU not using bus
Related: CPU, System Bus

Edge Cases & Gotchas

More bus arbitration overhead than burst mode — each transfer needs bus request/grant
If CPU is very active, DMA transfer can take a long time (many cycles “stolen”)
I/O device may underrun if DMA can’t keep up due to CPU bus usage

direct-addressing

2026-04-30T00:00:00.000Z

The Problem

We need to access specific memory locations (variables, data structures). Embedding the memory address directly in the instruction allows the CPU to access that fixed location.

Core Idea

Direct Addressing specifies the exact memory address of the operand within the instruction. The CPU reads/writes to that specific memory location.

How It Works

Instruction includes the memory address (e.g., 1234h)
CPU fetches the instruction, extracts the address
CPU performs a memory read/write to that address
Example: MOV AX, [1234h] — loads data from memory address 1234h into AX
Requires one memory access (in addition to instruction fetch)

Key Properties

Simple and intuitive — address is fixed at compile time
Limited address range: address size limited by instruction format
Used for accessing global variables, fixed data structures
Slower than register addressing (requires memory access)

Semantic Network

Connections

Built from: Addressing Mode, Memory Address
Contrasts with: Immediate Addressing — value in instruction, not address
Contrasts with: Indirect Addressing — address in register, not instruction
Related: Memory, Effective Address

Edge Cases & Gotchas

Address is fixed at compile time (can’t change at runtime)
Limited address range (e.g., 16-bit address = 64KB max)
Position-independent code can’t use direct addressing (addresses change)

dma-controller

2026-04-30T00:00:00.000Z

The Problem

The CPU should not waste cycles copying data between I/O devices and memory. But without a dedicated hardware controller, there’s no way to transfer data directly — someone (the CPU) must handle each byte.

Core Idea

The DMA Controller (DMAC) is a specialized hardware component that manages data transfers between I/O devices and memory without CPU intervention, using bus mastering to directly access memory.

How It Works

CPU programs the DMAC with: source address, destination address, transfer count
DMAC takes control of the system bus (bus arbitration)
DMAC generates memory addresses and transfer signals
Data moves directly between device and memory via DMAC
DMAC decrements count for each transfer, increments addresses
When count reaches zero, DMAC raises an interrupt to notify CPU

Key Properties

Contains registers for source address, destination address, transfer count, control
Can operate in different modes (burst, cycle stealing, transparent)
Requires bus arbitration logic to coordinate with CPU for bus access
Typically supports multiple channels for different devices

Semantic Network

Connections

Built from: System Bus, Device Controller
Builds into: DMA — DMAC is the hardware that implements DMA
Related: O Devices, Buffering
Contrasts with: CPU — DMAC handles transfers, CPU free to do other work

Edge Cases & Gotchas

Bus contention: CPU and DMAC both need bus access — arbitration required
Cache coherency: CPU cache may not see DMAC-written data (need cache flush/invalidate)
Wrong register programming (bad address/count) can corrupt memory
Some systems have limited DMA channels — resource contention possible

DMA Modes Comparison -- Burst vs Cycle Stealing vs Transparent

2026-04-30T00:00:00.000Z

The Comparison

DMA can operate in three different modes, each balancing transfer speed, CPU responsiveness, and implementation complexity differently.

Side-by-Side Comparison

Feature	Burst Mode	Cycle Stealing Mode	Transparent Mode
Transfer style	Entire block at once	One byte/word at a time	Only when CPU not using bus
CPU status	Paused/halted until DMA finishes	Can work between transfers	Never blocked
Transfer speed	Fastest (no interruptions)	Slower (bus arbitration per byte)	Slowest (limited by CPU idle time)
CPU responsiveness	Worst (completely blocked)	Good (can respond to interrupts)	Best (completely transparent)
Implementation	Simple	Moderate	Complex (needs bus monitoring)
Use case	High-priority, time-critical	General-purpose systems	Background transfers

Visual Timeline

Burst Mode: CPU → [██████ DMA ██████] → CPU Cycle Stealing: CPU → DMA → CPU → DMA → CPU → DMA → CPU Transparent: CPU → CPU → DMA → CPU → CPU → DMA → CPU

Key Insights

Burst Mode: Best for real-time systems where transfer speed matters more than CPU responsiveness. CPU is fully blocked.
Cycle Stealing: The most common mode — balances transfer speed with CPU responsiveness. CPU can handle interrupts between DMA transfers.
Transparent Mode: Zero CPU overhead, but slowest. Good for background tasks where completion time doesn’t matter.
Trade-off: Faster transfer = more CPU blocking. The system’s requirements determine which mode to use.

Visual Explanation

Semantic Network

Connections

Burst Mode DMA — entire block, CPU blocked
Cycle Stealing Mode DMA — one at a time, CPU works between
Transparent Mode DMA — only when CPU idle
DMA — the underlying mechanism
DMA Controller — hardware that implements these modes
CPU — affected differently by each mode

Big Endian vs Little Endian Comparison

2026-04-30T00:00:00.000Z

The Comparison

Big Endian and Little Endian are two conventions for storing multi-byte data in memory. The difference is which byte (Most Significant or Least Significant) gets stored at the lowest memory address.

Side-by-Side Comparison

Feature	Big Endian	Little Endian
Byte order	MSB → LSB (MSB first)	LSB → MSB (LSB first)
Human readability	Easier (matches usual notation)	Harder (reversed in memory dumps)
CPU examples	Motorola 68k, SPARC (sometimes)	Intel x86, AMD64
Network order	Standard (TCP/IP network byte order)	Not standard
Arithmetic efficiency	May need extra byte reordering	Efficient for x86 arithmetic (LSB first)
Debugging	Easier to read memory dumps	Harder to read memory dumps

Visual Example

For 32-bit number 0x12345678:

Big Endian (MSB first):

Address:  1000h  1001h  1002h  1003h
Data:      12     34     56     78

Little Endian (LSB first):

Address:  1000h  1001h  1002h  1003h
Data:      78     56     34     12

Key Insights

Network byte order: TCP/IP protocols mandate Big Endian (called “network byte order”). Little Endian systems must convert when sending data over network.
No “right” answer: Both have valid use cases. Big Endian matches human reading order; Little Endian is more efficient for x86 arithmetic.
Data corruption risk: Mixing systems with different endianness without conversion causes silent data corruption.
Most systems are Little Endian today: Intel x86 dominance made Little Endian the most common desktop/PC architecture.

Visual Explanation

Semantic Network

Connections

Big Endian — MSB first storage
Little Endian — LSB first storage
Endianness — the concept of byte order
Network Byte Order — Big Endian for TCP/IP
Memory — where bytes are stored
Multi-Byte Data — what endianness applies to

endianness

2026-04-30T00:00:00.000Z

The Problem

Multi-byte data (16-bit, 32-bit, 64-bit numbers) must be stored in memory as individual bytes. But which byte goes at the lowest memory address — the most significant or least significant byte?

Core Idea

Endianness defines the byte order used to store multi-byte data in memory: Big Endian puts the Most Significant Byte first; Little Endian puts the Least Significant Byte first.

How It Works

A 32-bit number like 0x12345678 has 4 bytes: 0x12 (MSB), 0x34, 0x56, 0x78 (LSB)
Big Endian stores: 12 34 56 78 at increasing memory addresses
Little Endian stores: 78 56 34 12 at increasing memory addresses
When reading multi-byte data, CPU must know the correct byte order
Mismatch between systems causes data corruption (e.g., network data on x86)

Key Properties

Big Endian: matches human reading order (easier to debug in memory dumps)
Little Endian: more efficient for CPU arithmetic (LSB processed first on x86)
Network protocols use Big Endian (called “network byte order”)
Intel x86/AMD use Little Endian; some RISC chips use Big Endian

Semantic Network

Connections

Built from: Memory, Multi-Byte Data
Contrasts with: Big Endian vs Little Endian — different byte orders
Related: Network Byte Order, Memory Address
Builds into: Data Serialization — must handle endianness when transferring data

Edge Cases & Gotchas

Endianness only matters for multi-byte data (byte-order sensitive)
Single bytes are not affected by endianness
Mixing systems with different endianness causes data corruption
Some CPUs are bi-endian (can switch mode) — software must track current mode

immediate-addressing

2026-04-30T00:00:00.000Z

The Problem

Some operands are constants (like initializing a register to 5). Having to store the constant in memory and then load it wastes time and memory. Can we put the constant directly in the instruction?

Core Idea

Immediate Addressing embeds the operand value directly inside the instruction itself. The CPU uses this constant value as-is, with no memory access needed.

How It Works

Instruction format: OPCODE + CONSTANT_VALUE
CPU fetches instruction from memory
Constant value is part of the instruction (in the operand field)
CPU uses the constant directly — no additional memory fetch
Example: MOV AX, 5 — moves the constant 5 into register AX

Key Properties

Fastest addressing mode (no memory access for operand)
Instruction is longer (includes the constant value)
Constant is fixed at compile time (can’t change at runtime)
Used for initializing registers, constants, small values

Semantic Network

Connections

Built from: Addressing Mode, Operand
Contrasts with: Direct Addressing — address in instruction, not value
Related: Register Addressing, Instruction Set
Builds into: Program Counter — instruction fetch includes immediate data

Edge Cases & Gotchas

Large constants make instructions longer (affects code size)
Constant can’t be changed at runtime (it’s part of the instruction)
Limited range: constant size limited by instruction format (e.g., 16-bit immediate)

indexed-addressing

2026-04-30T00:00:00.000Z

The Problem

Arrays and tables store data sequentially. Accessing array[i] requires computing address = base + i. Can the CPU compute this automatically during addressing?

Core Idea

Indexed Addressing computes the effective address by adding a base address (from instruction) and an index value (from a register). Perfect for accessing array elements and table lookups.

How It Works

Instruction specifies base address (e.g., 1000h) and index register (e.g., SI)
CPU reads index register to get offset value
Effective address = base address + index
CPU accesses memory at the computed address
Example: MOV AX, [1000h + SI] — SI is index, accesses memory at (1000h + SI)

Key Properties

Ideal for array access: base = array start, index = element offset
Index register can be incremented in loops (efficient array traversal)
Requires address computation (slightly slower than simpler modes)
Used in loops, array processing, table lookups

Semantic Network

Connections

Built from: Addressing Mode, Indirect Addressing
Related: Array, Loop, Effective Address
Builds into: Register Indirect with Displacement
Contrasts with: Direct Addressing — no index computation

Edge Cases & Gotchas

Index register must be set correctly before use (common bug: forgetting to increment)
Address calculation may overflow (base + index exceeds address space)
Requires more hardware (adder for address calculation)

indirect-addressing

2026-04-30T00:00:00.000Z

The Problem

Direct addressing uses a fixed address in the instruction. But what if the address isn’t known until runtime (e.g., pointers, dynamic memory)? We need a way to specify an address that can change.

Core Idea

Indirect Addressing specifies a register (or memory location) that holds the address of the operand. The CPU first reads the register to get the address, then accesses memory at that address.

How It Works

Instruction specifies a register (e.g., BX) that contains the address
CPU reads the register to get the memory address
CPU performs memory access using that address
Example: MOV AX, [BX] — BX holds address, CPU reads memory at (BX) and loads into AX
Requires two memory accesses: one for instruction, one for operand

Key Properties

Address can be computed at runtime (pointers, dynamic allocation)
Used for arrays, linked lists, pointers
Slower than direct addressing (extra register read, still needs memory access)
Foundation for more complex addressing modes (indexed, displacement)

Semantic Network

Connections

Built from: Addressing Mode, CPU Register
Contrasts with: Direct Addressing — fixed address in instruction
Builds into: Indexed Addressing, Register Indirect with Displacement
Related: Pointer, Memory Address

Edge Cases & Gotchas

Register must contain valid address (null/invalid pointer causes exception)
Two memory accesses: slower than direct addressing
Register value can change at runtime (unlike direct addressing)

instruction-set

2026-04-30T00:00:00.000Z

The Problem

Software needs a way to tell the CPU what to do. The set of operations a CPU supports defines what programs can do and how efficiently they run.

Core Idea

The instruction set is the complete collection of machine-level instructions that a CPU can execute — it defines the boundary between software and hardware.

How It Works

Each instruction specifies an operation (add, load, branch, etc.) and operands (registers, memory addresses, constants)
CPU fetches instructions from memory, decodes them, and executes them
Instruction set architecture (ISA) defines: instruction formats, registers, memory model, addressing modes
Compiler translates high-level code to instructions in this set
RISC has few simple instructions; CISC has many complex ones

Key Properties

Defines CPU’s machine language (binary encoding of instructions)
RISC: small, simple, fixed-length; CISC: large, complex, variable-length
Includes data movement, arithmetic, logic, control flow instructions
ISA is a contract — software depends on it, hardware implements it

Semantic Network

Connections

Built from: CPU, Addressing Mode
Builds into: RISC Architecture, CISC Architecture
Related: ISA, Compiler
Contrasts with: Different ISAs are not directly compatible (x86 vs ARM)

Edge Cases & Gotchas

ISA is not implementation — two CPUs with same ISA can have different performance
Backward compatibility: new CPUs must support old ISA (lots of legacy baggage)
Modern CPUs may add extensions (SSE, AVX, NEON) to base ISA