DMA can operate in three different modes, each balancing transfer speed, CPU responsiveness, and implementation complexity differently.
| Feature | Burst Mode | Cycle Stealing Mode | Transparent Mode |
|---|---|---|---|
| Transfer style | Entire block at once | One byte/word at a time | Only when CPU not using bus |
| CPU status | Paused/halted until DMA finishes | Can work between transfers | Never blocked |
| Transfer speed | Fastest (no interruptions) | Slower (bus arbitration per byte) | Slowest (limited by CPU idle time) |
| CPU responsiveness | Worst (completely blocked) | Good (can respond to interrupts) | Best (completely transparent) |
| Implementation | Simple | Moderate | Complex (needs bus monitoring) |
| Use case | High-priority, time-critical | General-purpose systems | Background transfers |
Burst Mode: CPU → [██████ DMA ██████] → CPU Cycle Stealing: CPU → DMA → CPU → DMA → CPU → DMA → CPU Transparent: CPU → CPU → DMA → CPU → CPU → DMA → CPU
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Burst Mode: Best for real-time systems where transfer speed matters more than CPU responsiveness. CPU is fully blocked.
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Cycle Stealing: The most common mode — balances transfer speed with CPU responsiveness. CPU can handle interrupts between DMA transfers.
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Transparent Mode: Zero CPU overhead, but slowest. Good for background tasks where completion time doesn’t matter.
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Trade-off: Faster transfer = more CPU blocking. The system’s requirements determine which mode to use.
- Burst Mode DMA — entire block, CPU blocked
- Cycle Stealing Mode DMA — one at a time, CPU works between
- Transparent Mode DMA — only when CPU idle
- DMA — the underlying mechanism
- DMA Controller — hardware that implements these modes
- CPU — affected differently by each mode