DMA transfers need to balance between fast data movement and not blocking the CPU. If the DMA controller transfers too slowly, the I/O device may underrun; if it hogs the bus, the CPU can’t work.
Burst Mode DMA transfers the entire block of data in one continuous operation, with the DMA controller holding exclusive control of the system bus until the transfer completes.
- DMA controller requests and gains exclusive bus control
- Entire data block is transferred continuously, one word/byte at a time
- CPU is paused/halted during the entire transfer — cannot access memory or bus
- When transfer completes, DMA releases the bus and sends interrupt to CPU
- Fastest DMA mode for the transfer itself — no interruptions
- CPU is completely blocked during transfer (can’t even access cache if it misses)
- Best for high-priority, time-sensitive transfers (real-time systems)
- Simple to implement — no need for interleaving logic
- Built from: DMA, DMA Controller
- Contrasts with: Cycle Stealing Mode DMA — CPU can work between transfers
- Contrasts with: Transparent Mode DMA — DMA only runs when CPU not using bus
- Related: Polling — CPU also blocked in polling, but for different reasons
- Long bursts can cause CPU starvation — system becomes unresponsive
- Not suitable for systems requiring low-latency CPU response
- Some systems limit maximum burst size to prevent excessive CPU blocking
- Cache coherency issues still apply — CPU cache may be stale after burst